The first signal is rarely clean
Early engineering lots expose incomplete recipes, module interactions, and tool-state assumptions. A single wafer map rarely explains the failure mode on its own.
The goal is to build a signal that survives the noise. That starts with a sampling plan that separates random defectivity from repeatable process signatures.
Pareto reviews need ownership
A defect Pareto is only useful when each major bucket has an owner, a short-loop experiment, and a due date. Otherwise, the chart becomes a status artifact instead of a yield tool.
SILICON assigns defect classes back to module teams quickly, then uses metrology and FA results to confirm whether the proposed fix changes the curve.
Learning rate is a manufacturing metric
Yield ramp is often described as a product milestone, but the useful measure is learning rate. How quickly can the line turn defect knowledge into a lower excursion rate?
That cadence determines whether a 2nm flow exits pilot as a stable process or as a collection of individually solved issues.
